Scaling algorithm designed to reduce circuit costs for modular digital filters

Currently, there is a tendency to increase the speed and accuracy of data processing in computer networks (CN). It is possible to meet these requirements through the use of new technologies in CN telecommunication devices that rely on residue class codes (RNS). In these codes, input values are prese...

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मुख्य लेखकों:	Kalmykov, I. A., Калмыков, И. А., Sidorov, N. S., Сидоров, Н. С.
स्वरूप:	Статья
भाषा:	English
प्रकाशित:	IOP Publishing Ltd 2020
विषय:	Codes (symbols) Timing circuits Digital filters Data handling Cost reduction Digital signal processing
ऑनलाइन पहुंच:	https://dspace.ncfu.ru/handle/20.500.12258/14676
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spelling	ir-20.500.12258-146762020-12-09T13:37:21Z Scaling algorithm designed to reduce circuit costs for modular digital filters Kalmykov, I. A. Калмыков, И. А. Sidorov, N. S. Сидоров, Н. С. Codes (symbols) Timing circuits Digital filters Data handling Cost reduction Digital signal processing Currently, there is a tendency to increase the speed and accuracy of data processing in computer networks (CN). It is possible to meet these requirements through the use of new technologies in CN telecommunication devices that rely on residue class codes (RNS). In these codes, input values are presented as sets of remainder moduli of the RNS base selected. As a result, arithmetic operations are performed in parallel, which provides an increased speed of signal processing. Therefore, RNS codes are used in high-speed modular digital filters (MDF). To advance the accuracy of digital signal processing in MDF, the number of RNS bases is increased, which leads to greater circuit costs. It is possible to remedy this shortcoming by scaling an MDF response. Hence, it is crucial to develop a scaling algorithm to reduce circuit costs for MDF implementation 2020-12-09T13:35:43Z 2020-12-09T13:35:43Z 2020 Статья Kalmykov, I.A., Sidorov, N.S., Tyncherov, K.T., Vorohov, A.A. Scaling algorithm designed to reduce circuit costs for modular digital filters // Journal of Physics: Conference Series. - 2020. - Volume 1661. - Issue 1. - Номер статьи 012045 http://hdl.handle.net/20.500.12258/14676 en Journal of Physics: Conference Series application/pdf IOP Publishing Ltd
institution	СКФУ
collection	Репозиторий
language	English
topic	Codes (symbols) Timing circuits Digital filters Data handling Cost reduction Digital signal processing
spellingShingle	Codes (symbols) Timing circuits Digital filters Data handling Cost reduction Digital signal processing Kalmykov, I. A. Калмыков, И. А. Sidorov, N. S. Сидоров, Н. С. Scaling algorithm designed to reduce circuit costs for modular digital filters
description	Currently, there is a tendency to increase the speed and accuracy of data processing in computer networks (CN). It is possible to meet these requirements through the use of new technologies in CN telecommunication devices that rely on residue class codes (RNS). In these codes, input values are presented as sets of remainder moduli of the RNS base selected. As a result, arithmetic operations are performed in parallel, which provides an increased speed of signal processing. Therefore, RNS codes are used in high-speed modular digital filters (MDF). To advance the accuracy of digital signal processing in MDF, the number of RNS bases is increased, which leads to greater circuit costs. It is possible to remedy this shortcoming by scaling an MDF response. Hence, it is crucial to develop a scaling algorithm to reduce circuit costs for MDF implementation
format	Статья
author	Kalmykov, I. A. Калмыков, И. А. Sidorov, N. S. Сидоров, Н. С.
author_facet	Kalmykov, I. A. Калмыков, И. А. Sidorov, N. S. Сидоров, Н. С.
author_sort	Kalmykov, I. A.
title	Scaling algorithm designed to reduce circuit costs for modular digital filters
title_short	Scaling algorithm designed to reduce circuit costs for modular digital filters
title_full	Scaling algorithm designed to reduce circuit costs for modular digital filters
title_fullStr	Scaling algorithm designed to reduce circuit costs for modular digital filters
title_full_unstemmed	Scaling algorithm designed to reduce circuit costs for modular digital filters
title_sort	scaling algorithm designed to reduce circuit costs for modular digital filters
publisher	IOP Publishing Ltd
publishDate	2020
url	https://dspace.ncfu.ru/handle/20.500.12258/14676
work_keys_str_mv	AT kalmykovia scalingalgorithmdesignedtoreducecircuitcostsformodulardigitalfilters AT kalmykovia scalingalgorithmdesignedtoreducecircuitcostsformodulardigitalfilters AT sidorovns scalingalgorithmdesignedtoreducecircuitcostsformodulardigitalfilters AT sidorovns scalingalgorithmdesignedtoreducecircuitcostsformodulardigitalfilters
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Scaling algorithm designed to reduce circuit costs for modular digital filters

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