Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system

Convolutional Neural Networks (CNN) is the promising tool for solving task of image recognition in computer vision systems. However, the most known implementation of CNNs require a significant amount of memory for storing weights in training and work. To reduce the resource costs of CNN implementati...

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Auteurs principaux:	Chervyakov, N. I., Червяков, Н. И., Lyakhov, P. A., Ляхов, П. А., Valueva, M. V., Валуева, М. В., Valuev, G. V., Валуев, Г. В.
Format:	Статья
Langue:	English
Publié:	IEEE Computer Society 2019
Sujets:	Computer hardware Convolution Cost reduction Image recognition MATLAB Neural networks Numbering systems Field programmable gate arrays (FPGA)
Accès en ligne:	https://www.scopus.com/record/display.uri?eid=2-s2.0-85061049082&origin=resultslist&sort=plf-f&src=s&st1=%09Area-Efficient+FPGA+Implementation+of+Minimalistic+Convolutional+Neural+Network+Using+Residue+Number+System&st2=&sid=5de745aaf0b399b11edbcdbf364e241e&sot=b&sdt=b&sl=123&s=TITLE-ABS-KEY%28%09Area-Efficient+FPGA+Implementation+of+Minimalistic+Convolutional+Neural+Network+Using+Residue+Number+System%29&relpos=0&citeCnt=0&searchTerm= https://dspace.ncfu.ru/handle/20.500.12258/4353
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spelling	ir-20.500.12258-43532020-07-29T13:07:59Z Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system Chervyakov, N. I. Червяков, Н. И. Lyakhov, P. A. Ляхов, П. А. Valueva, M. V. Валуева, М. В. Valuev, G. V. Валуев, Г. В. Computer hardware Convolution Cost reduction Image recognition MATLAB Neural networks Numbering systems Field programmable gate arrays (FPGA) Convolutional Neural Networks (CNN) is the promising tool for solving task of image recognition in computer vision systems. However, the most known implementation of CNNs require a significant amount of memory for storing weights in training and work. To reduce the resource costs of CNN implementation we propose the architecture that separated on hardware and software parts for performance optimization. Also we propose to use Residue Number System (RNS) arithmetic in the hardware part which implements the convolutional layer of CNN. Software simulation using Matlab 2017b shows that CNN with a minimum number of layers can be quickly and successfully trained. Hardware simulation using FPGA Kintex7 xc7k70tfbg484-2 demonstrates that using RNS in convolutional layer of CNN allows to reduce hardware costs by 32% compared with the traditional approach based on the binary number system 2019-02-18T11:50:00Z 2019-02-18T11:50:00Z 2018 Статья Chervyakov, N.I., Lyakhov, P.A., Valueva, M.V., Valuev, G.V., Kaplun, D.I., Efimenko, G.A., Gnezdilov, D.V. Area-Efficient FPGA Implementation of Minimalistic Convolutional Neural Network Using Residue Number System // Conference of Open Innovation Association, FRUCT. - 2018. - Volume 2018-November. - Номер статьи 8588106. - Pages 112-118 https://www.scopus.com/record/display.uri?eid=2-s2.0-85061049082&origin=resultslist&sort=plf-f&src=s&st1=%09Area-Efficient+FPGA+Implementation+of+Minimalistic+Convolutional+Neural+Network+Using+Residue+Number+System&st2=&sid=5de745aaf0b399b11edbcdbf364e241e&sot=b&sdt=b&sl=123&s=TITLE-ABS-KEY%28%09Area-Efficient+FPGA+Implementation+of+Minimalistic+Convolutional+Neural+Network+Using+Residue+Number+System%29&relpos=0&citeCnt=0&searchTerm= http://hdl.handle.net/20.500.12258/4353 en Conference of Open Innovation Association, FRUCT application/pdf application/pdf IEEE Computer Society
institution	СКФУ
collection	Репозиторий
language	English
topic	Computer hardware Convolution Cost reduction Image recognition MATLAB Neural networks Numbering systems Field programmable gate arrays (FPGA)
spellingShingle	Computer hardware Convolution Cost reduction Image recognition MATLAB Neural networks Numbering systems Field programmable gate arrays (FPGA) Chervyakov, N. I. Червяков, Н. И. Lyakhov, P. A. Ляхов, П. А. Valueva, M. V. Валуева, М. В. Valuev, G. V. Валуев, Г. В. Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system
description	Convolutional Neural Networks (CNN) is the promising tool for solving task of image recognition in computer vision systems. However, the most known implementation of CNNs require a significant amount of memory for storing weights in training and work. To reduce the resource costs of CNN implementation we propose the architecture that separated on hardware and software parts for performance optimization. Also we propose to use Residue Number System (RNS) arithmetic in the hardware part which implements the convolutional layer of CNN. Software simulation using Matlab 2017b shows that CNN with a minimum number of layers can be quickly and successfully trained. Hardware simulation using FPGA Kintex7 xc7k70tfbg484-2 demonstrates that using RNS in convolutional layer of CNN allows to reduce hardware costs by 32% compared with the traditional approach based on the binary number system
format	Статья
author	Chervyakov, N. I. Червяков, Н. И. Lyakhov, P. A. Ляхов, П. А. Valueva, M. V. Валуева, М. В. Valuev, G. V. Валуев, Г. В.
author_facet	Chervyakov, N. I. Червяков, Н. И. Lyakhov, P. A. Ляхов, П. А. Valueva, M. V. Валуева, М. В. Valuev, G. V. Валуев, Г. В.
author_sort	Chervyakov, N. I.
title	Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system
title_short	Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system
title_full	Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system
title_fullStr	Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system
title_full_unstemmed	Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system
title_sort	area-efficient fpga implementation of minimalistic convolutional neural network using residue number system
publisher	IEEE Computer Society
publishDate	2019
url	https://www.scopus.com/record/display.uri?eid=2-s2.0-85061049082&origin=resultslist&sort=plf-f&src=s&st1=%09Area-Efficient+FPGA+Implementation+of+Minimalistic+Convolutional+Neural+Network+Using+Residue+Number+System&st2=&sid=5de745aaf0b399b11edbcdbf364e241e&sot=b&sdt=b&sl=123&s=TITLE-ABS-KEY%28%09Area-Efficient+FPGA+Implementation+of+Minimalistic+Convolutional+Neural+Network+Using+Residue+Number+System%29&relpos=0&citeCnt=0&searchTerm= https://dspace.ncfu.ru/handle/20.500.12258/4353
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Area-efficient FPGA implementation of minimalistic convolutional neural network using residue number system

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